Staff Design Verification Engineer (Toronto)
May 31
🔄 Hybrid – Toronto
Description
• Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans. • Design and implement UVM testbenches for both subsystem-level and full-chip verification. This includes debugging testbenches, resolving issues, achieving high coverage, and overseeing the final sign-off on Design Verification (DV). • Develop Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM, and ensure precise model representation. Contribute significantly to the development of the Golden Reference Model (GRM) for design verification. Play an integral role in the execution of emulation and formal verification for DV purposes.
Requirements
• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience • 5-10 years of design verification and SystemVerilog experience • 2+ years of experience in python • Expertise in developing with the UVM library • Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
Benefits
• Comprehensive Health Care Plan • Group Retirement Savings Plan matching • Life Insurance • Generous Time Off (Vacation, Sick & Public Holidays) • Training & Development • Flexible, hybrid workplace model • Stock Option Plan
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